“For several decades, the advancement of monolithic systems-on-chip (SoCs) for high-performance computing (HPC) – such as CPUs and GPUs – hinged on the success of CMOS scaling,” says Ryckaert, “CMOS offered SoC developers a technology platform that allowed them to integrate more and more functions on one and the same substrate. Even with the evolution towards multi-core architectures, it turned out more efficient to integrate every function on a common substrate than to move data around between different chips.” ”In addition, the SoC’s power, performance, area, and cost (PPAC) could be improved just by scaling the transistors and the interconnects from one node to another.
The most scaled technology was applied in every functional part of the SoC – from computing blocks to cache memory to the infrastructure that wraps the system (including electrostatic discharge (ESD) protection devices, power and clock distribution, signal networks, and input/outputs (I/O)).” “For a long time, this CMOS platform served different computational needs, for mobile applications as well as for HPC. But this general-purpose technology platform gradually began to break, for two reasons.
First, dimensional scaling started to provide diminished PPAC returns at the system level. Second, the once praised heterogeneity of the SoC – created by adding more and more functions in a 2D fashion – progressively became its own bottleneck: with only one technology at hand to build all t.